The present invention relates to integrated circuit contact and interconnect technology and more particularly to the use of refractory metals in the formation of contacts and shunts. In particular, the present invention teaches an integrated fabrication process for forming contacts and shunts without regard to the impurity type of semiconductor regions being connected.
Metallization technology presently includes three broad areas: aluminum metallization processes; refractory metal processes, including those using tungsten; and composite layer processes, in which two or more separate conductors are deposited sequentially and then etched coextensively to the desired pattern. Each of these three approaches has advantages and disadvantages which are, typically, unique to the selected technology area.
Consider first the prevalent aluminum metallization technology. Aluminum, or aluminum alloyed with a small percentage of silicon and/or copper, has been the standard microelectronics interconnect metallization for a number of years. Accordingly, aluminum has the advantage of being very well characterized. However, as device component thicknesses and lateral dimensions are made increasingly smaller in progressing from LSI to VLSI technologies, and beyond, the disadvantages of aluminum--the difficulty in etching small geometry aluminum lines, electromigration susceptibility at small geometries, and aluminum spiking of shallow junctions--have become major impediments to its continued use. One technique for using aluminum to interconnect oppositely doped layers and regions is described in U.S. Pat. No. 4,322,736 to inventors Sasaki et al. Given the limited temperature capabilities of aluminum, this teaching corresponds in most respects to the contact forming techniques routinely used in the concluding stages of integrated circuit fabrication.
The limited temperature capabilities of aluminum, and the low adhesion capabilities of evaporated or sputtered refractory metal films, such as tungsten films, to silicon dioxide has in recent times lead to the development of techniques by which such films are selectively deposited. A representative investigation is described in Miller et al. "CVD Tungsten Interconnect and Contact Barrier Technology for VLSI", Solid State Technology, December 1982, pp. 85-90. Miller et al. discusses the need for new materials and deposition processes for VLSI technology in the areas of contact barriers, low resistance gates and alternative metallization techniques. Low resistance contact barriers of refractive metal are proposed to prevent aluminum spiking through shallow, scaled junctions. Exemplary barriers include the more common Ti-W over platinum silicide and Ti-W over palladium silicide, along with a proposed CVD tungsten barrier technique. The Miller et al., article considers silicide shunts and composite Ti-W over silicide contact barriers, and proposes the substitution of CVD tungsten for such materials in contact barriers and low resistance shunt applications, as well as for aluminum metallization. Similar techniques are described in Moriya et al., "A Planar Metallization Process - Its Application to Tri-Level Aluminum Interconnection," IEDM 1983, Paper 25.3, pp. 550-552, and in the paper entitled "Low Pressure Chemical Vapor Deposition of Metals and Their Application in VLSI Technology," presented by E.K. Broadbent at the Electrochemical Society Meeting in Washington, D.C. on Oct. 9-14, 1983.
These articles and presentations do not suggest using a patterned layer of very thin conformally deposited intrinsic polysilicon or amorphous silicon to define the selectively deposited tungsten metallization pattern; nor the use of updiffusion from diffused substrate regions to form self-aligned contacts joining the tungsten metal layer to the diffused subtrate regions; nor the use of tungsten reduction of such conformally deposited intrinsic polysilicon or amorphous silicon to form self-aligned, low resistance, ohmic contacts; nor the combination of these contact and metallization techniques into a unitary contact and metallization process based solely upon the use of patterned silicon, irrespective of the impurity type of the joined regions, to define the interconnect, shunt and contact patterns.
Further examples of metallization techniques employing refractory metals or their silicides are described in U.S. Pat. No. 4,333,099 to inventors Tanguay et al.; U.S. Pat. No. 4,276,688 to inventor Hsu; U.S. Pat. NO. 4,330,931 to inventor Lui; and U.S. Pat. No. 4,374,700 to inventors Scott et al. The first two patents relate to the use of sputtered and patterned platinum and molybdenum refractory metals to form at correspondingly disposed silicon locations silicides which bridge p-n junctions or buried contacts for silicon on sapphire type CMOS structures. U.S. Pat. No. 4,330,931 describes the use of selectively deposited tungsten to plate regions of monocrystalline and polycrystalline silicon, and particularly on the gate, source and drain electrode regions of field effect transistors. According to the teaching in the fourth of the last noted U.S. Pat. No., 4,374,700 to Scott et al., silicides are used to bridge the gate oxide layers in a polysilicon interconnect structure. The silicide provides ohmic contact without regard to the impurity type of the interconnected regions.
Consider next the composite or multiple layer conductor approach for contacts formation and/or metallization. This technology includes a number of different structures, including for example polycide (a metal silicide over polycrystalline silicon) and the above-mentioned titanium-tungsten (Ti-W) over metal silicide layers. The multiple layer approach provides the opportunity to compensate for the undesirable characteristics of individual materials or compounds. For example, the composite structure of tungsten on polysilicon uses the tungsten to decrease the sheet resistance, while the underlying polysilicon provides the adhesion required to traverse dielectric materials such as silicon dioxide, which adhesion is not available from tungsten alone. However, typically, multiple layer prior art structures involve considerable processing complexity in sequentially forming and coextensively patterning the layers.
One such prior art approach, involving a composite silicon-nickel-lead contact system for bipolar integrated circuits, is disclosed in Denning, U.S. Pat. No. 3,632,436, issued Jan. 4, 1972. In a representative process sequence therefrom, a passivating layer is formed over the bipolar device wafer and is etched to provide emitter and base contact cuts. Then, a layer of silicon is blanket deposited onto both the insulator and the exposed substrate contact regions, and is thereafter masked and etched to provide the desired contact/conductor pattern. The nickel layer of the composite is selectively formed on the silicon base conductor by electroless plating, that is, by immersion in an electroless plating bath, followed by sintering to enhance the nickel adhesion to the silicon. Thereafter, the lead layer is formed on the nickel by dipping the structure in a molten lead solder bath. While the Denning patent discloses a composite contact system, the process is complicated in its use of electroless plating and molten solder baths. No shunting of differently doped simiconductor regions is taught or suggested. Furthermore, it seems doubtful whether the techniques are at all meaningful to current or future microelectronics processes.
Hall, U.S. Pat. No. 4,042,953, issued Aug. 16, 1977; U.S. Pat. No. 4,152,823, issued May 8, 1979; and U.S. Pat. No. 4,265,935, issued May 5, 1981, all relate to a refractory metal contact/interconnect fabrication techniques. Representative completed structures are comprised of a layer of high temperature inert refractory metal, such as molybdenum, tungsten, platinum, nickel or palladium, sandwiched between upper and lower silicon layers. In one application, the refractory metal sandwich composite is used to provide ohmic contact between a semiconductor substrate and a metal interconnect. In a second application, the composite forms MOSFET gate electrodes and interconnects.
For the contact application, the two silicon layers provide ohmic contact between the substrate and the refractory metal and between the refractory metal and the metal interconnect. A typical fabrication sequence involves forming a thick isolation oxide layer on the substrate and defining contact cuts therein, then sputter depositing the silicon and refractory metal, etching the metal to an interconnect pattern and thereafter sputter depositing the second silicon layer.
In the gate electrode/interconnect application, the refractory sandwich assembly is first blanket deposited layer by layer in a composite of silicon, refractory metal, and silicon over the gate oxide and field oxide, then is etched to the electrode/interconnect pattern desired. However, representative structures as depicted in FIGS. 3 and 4 of the Hall patents disclose arrangements in which the sandwiched gate electrode metallization is actually shorted to both the source and drain diffusions. More importantly in regard to the present invention, neither this second application nor the first suggests using a patterned layer of very thin conformally deposited intrinsic polysilicon or amorphous silicon to define the selectively deposited tungsten metallization pattern; nor the use of updiffusion from the substrate to form contacts; nor reduction of silicon by tungsten to form ohmic contacts; nor the combination of these contact and metallization techniques into a unitary contact and metallization process based solely upon the tungsten and silicon structure.
Still another three layer refractory metal composite is disclosed in Widmann, U.S. Pat. No. 4,356,622, issued Nov. 2, 1982. The Widmann three layer composite is a polysilicon, silicide, and oxide structure which performs three functions. First, the doped polysilicon layer serves as an impurity source for forming the source and drain regions. Secondly, the metal silicide intermediate layer decreases the sheet resistance of the underlying diffused source/drain regions. Thirdly, the oxide top layer prevents short circuits between the source/drain structure and the adjacent gate electrode.
Again, while the Widmann patent uses tungsten on silicon in the multiple purpose composite, there is no suggestion of using a patterned layer of very thin conformally deposited intrinsic polysilicon or amorphous silicon to define the selectively deposited tungsten metallization pattern; nor the use of updiffusion from the substrate to form contacts; nor reduction of silicon by tungsten to form ohmic contacts; nor the combination of these contact and metallization techniques into a unitary contact and metallization process based solely upon the tungsten and silicon structure.
Another approach to the use of tungsten in decreasing contact resistance, involving the prevention of silicide formation, is disclosed in Gargini et al., "WOS: Low Resistance Self-Aligned, Source, Drain and Gate Transistors", IEDM 1981, Paper 3.2, pp. 54-57. Using the Gargini et al. approach, the contact resistance to both silicon and polysilicon is decreased by the use of a selectively formed tungsten layer at the contact region. The gate oxide and the polysilicon gate electrode are defined in the active region and tungsten is selectively deposited to a thickness of about 150 nanometers on the doped gate electrode and the exposed doped substrate source/drain regions, preferably by chemical vapor deposition using WF.sub.6 and H.sub.2. A low temperature, plasma assisted chemical vapor deposition process is then used to form a silicon nitride interlayer dielectric for the aluminum metallization, following which contact cuts are formed and the metallization is applied. The use of silicon nitride avoids the typical use of a high temperature phosphorus doped oxide as the interlayer dielectric, and thereby avoids silicide formation with the underlying silicon at the temperatures normally used to reflow this oxide. In short, while the Gargini et al. approach does use the selective deposition of tungsten on silicon to decrease contact resistance to aluminum interconnects, there is no suggestion of using a patterned layer of very thin conformally deposited intrinsic polysilicon or amorphous silicon to define the selectively deposited tungsten metallization pattern; nor the use of updiffusion from the substrate to form contacts; nor reduction of silicon by tungsten to form ohmic contacts; nor the combination of these contact and metallization techniques into a unitary contact and metallization process based solely upon the tungsten and silicon structure.
The application of selectively deposited tungsten in combination with or distinct from aluminum to shunt polysilicon and monocrystalline silicon regions appears in U.S. Pat. No. 4,441,247 to inventors Gargini et al. However, as was true of the immediately preceding article, there appears no teaching of using a patterned layer of very thin conformally deposited intrinsic polysilicon or amorphous silicon to define the selectively deposited tungsten metallization pattern; nor the use of updiffusion from the substrate to form contacts; nor reduction of silicon by tungsten to form ohmic contacts; nor the combination of these contact and metallization techniques into a unitary contact and metallization process based solely upon the tungsten and silicon structure.
In view of the above discussion, it is one object of the present invention to provide a uniquely abridged process for forming a composite metallization layer comprising a thin layer of patterned intrinsic polysilicon or amorphous silicon together with a shunting tungsten layer.
Another object of the present invention is to provide a process for fabricating low resistance, self-aligned, ohmic contacts to substrate diffusion regions.
Still another object of the present invention is to provide a process for fabricating low resistance, self-aligned, ohmic contacts to substrate diffusion regions as part of a unitary process for forming integrated circuit metallization using a common composite structure and with a minimum number of additional processing operations.
It is also an object to provide a contact metallization process which is suitable for forming self-aligned, ohmic contacts to both n-type and p-type silicon, without preference or selectivity.